The present invention relates to a method of manufacturing non-volatile memory devices. Although not limiting, the present invention relates in particular to a method for improving the planarity of semiconductor integrated electronic devices, such as the polysilicon gate electrode defined during the manufacturing process of the non-volatile memory. The following description makes reference to this field of application for convenience of illustration only.
As is well known to those skilled in the art, electronic non-volatile memory devices, such as flash memories, for example, are integrated in a semiconductor substrate and comprise a plurality of non-volatile memory cells arranged as an array. Specifically, the array is made up of rows (or wordlines) and columns (or bitlines).
Each non-volatile memory cell comprises a MOS transistor having a floating gate electrode. The floating gate electrode is located above a channel region, and has a high DC impedance to the other terminals of both the memory cell and of the host circuit for the memory cell.
The memory cell has a second or gate control electrode capacitively coupled to the floating gate electrode through an intermediate dielectric layer, known as an interpoly layer. The second electrode of the memory cell is driven by appropriate control voltages. Other transistor electrodes of the memory cell are the drain and source terminals.
In general, the memory cell array has associated therewith control circuitry that includes a conventional MOS transistor, which has source and drain regions separated by a channel region. A gate electrode is also formed over the channel region and is isolated from the latter by a gate oxide layer.
The process steps for manufacturing a memory array and its circuitry includes forming active areas for the memory array and circuitry; growing an active oxide layer (known as the tunnel oxide) over the active areas; and depositing a first polysilicon layer on the whole device.
The process further includes defining floating gate electrodes in the array region; depositing a dielectric or interpoly layer, e.g., ONO (Oxide/Nitrate/Oxide); and forming a photolithographic mask, referred to as the MATRIX mask, on the memory array for etching through the interpoly layer and the first polysilicon layer of the circuitry.
The process further includes growing one or more active gate oxides over both the circuitry and the memory array; depositing a second polysilicon layer; defining the control gate electrodes of the array cells in the second polysilicon layer by exposing through a SAE (Self-Aligned Etch) mask; defining the gate electrodes of the transistors in the circuitry by exposing through the circuitry mask; and forming the transistor source and drain regions and metal layers.
In this way, the memory cell transistors comprise two polysilicon layers which are formed thicker than the circuitry transistors. In particular, when memory devices are formed with technologies that effectively define dimensions of 0.15 xcexcm or less, the difference in thickness between the array regions where the memory cells are formed and the circuitry regions where the control devices are formed becomes more and more substantial.
In particular, the thickness of the second polysilicon layer, which is deposited on the first polysilicon layer to form the control gate electrodes of the memory cells and the gate electrodes of the circuitry transistors formed simultaneously therein, will be much smaller then the combined layers that are deposited to form a memory cell.
In a flash memory cell, the overall thickness of the stack structure, which includes the tunnel oxide layer, the first polysilicon layer, the interpoly dielectric layer, and the second polysilicon layer may be approximately 4100 xc3x85. A thickness of the stack structure of the circuitry, which includes the gate oxide layer and the second polysilicon layer is approximately 2600 xc3x85.
Therefore, the array has a thickness increase of about 1500 xc3x85 over the circuitry area. This difference creates a xe2x80x9cstepxe2x80x9d between the array and the circuitry structure, which does not allow for a uniform spread over the device regions of subsequently applied layers, such as anti-reflective BARC layers or light-sensitive material layers used to define the polysilicon layers of the memory cells.
On account of these thickness differences on the device, some regions of uniform thickness will be formed where the required lithographic dimensions can be correctly defined for the memory cells, and some regions of non-uniform thickness will be formed where local lithographic focusing problems can be observed. The result is a memory cell gate electrode whose dimensions are different from the specification, such as being narrower than is required for proper performance of the device.
In this situation, reliability of the device is lost in significant amounts, and is enough to induce rejection of the device which results in an increase in the yield loss during the testing stage. It can be appreciated, therefore, that a difference in thickness between circuit structures can hinder (dimension-wise) a correct definition of each portion in the broad region where the memory array is formed. As just mentioned, this difference in thickness can be due to different steps of the manufacturing process.
The underlying technical problem of the present invention is to provide a method of manufacturing circuit structures having features appropriate for ensuring a uniform thickness over several portions of an electronic circuit, and to overcome the limitations and/or shortcomings of the prior devices.
The method of the present invention is one of carrying out an etching step on circuit structures having a greater thickness than the other circuit structures, whereby the thickness of the former can be reduced and made uniform with the thickness of the integrated circuit.
The method of manufacturing a non-volatile memory device in accordance with the present invention comprises depositing a first layer on a semiconductor substrate, selectively removing a portion of the first layer to form a memory array area, and depositing a second layer on the memory array area and on adjacent areas of the semiconductor substrate contacting the memory array area. The second layer may have a thickness that is substantially equal over the memory array area and over the adjacent areas. The method may further include forming a screening layer on the second layer on the adjacent areas except for outer peripheral portions thereof adjacent the memory array area. The thickness of the second layer exposed on the memory array area and on the outer peripheral portions of the adjacent areas is reduced so that an upper surface thereof is substantially coplanar with an upper surface of the second layer on the adjacent areas.
A dry etching may be used to reduce the thickness of the second layer. The method may further comprise removing the screening layer, and the remaining outer peripheral portions of the adjacent areas form protrusions that serve as barriers for the memory array area when subsequent layers are formed.
A dielectric layer may be formed on the semiconductor substrate before the first layer is formed, and another dielectric layer may be formed on the first layer before the second layer is formed. The first and second layers may each comprise a polysilicon layer. The method may further comprise forming in the first layer of the memory array area floating gate regions for memory cells, and forming in the second layer of the memory array area control gate regions for the memory cells.